Delay compensation in bilateral teleoperation using predictor observers

Destabilization and performance degradation problems caused by the time delay in communication channel is a serious problem in bilateral teleoperation. In particular, variability of the delay due to limited bandwidth, long distance or congestion in transmission problems has been a real challenge in bilateral teleoperation research since the internet communication has become prevalent. Many existing delay compensation techniques are designed for linear teleoperator systems. In order to implement them on real bilateral systems, the nonlinear dynamics of the robots must first be linearized. For this purpose feedback linearization is usually employed. In this thesis, the delay compensation problem is tackled in an observer framework by designing two observers. Integration of a disturbance observer to the slave side implies a linearized slave dynamics with nominal parameters. Disturbance observer estimates the total disturbance (nonlinear terms, parametric uncertainties and external disturbances) on the slave system. A second observer is designed at the master side to predict states of the slave. This observer can be designed using a variety of linear or nonlinear methods. In order to have finite-time convergence, a sliding mode observer is designed at the master side. It is shown that this observer predicts the future positions and/or velocities of the slave and use of such predictions in the computation of a simple PD control law implies stable operation for the bilateral system. Since the disturbance observer increases the robustness of the slave system, the performance of the resulting bilateral system is quite satisfactory. Force reflecting bilateral teleoperation is also considered in this thesis. Integrating the proposed observer based delay compensation technique into the well known four-channel control architecture not only stable but also transparent bilateral teleoperation is achieved. Simulations with bilateral systems consisting of 2 DOF scara robots and pantograph robots, and experiments with bilateral systems consisting of a pair of single link robots and a pair of pantograph robots validate the proposed method

Delay compensation for nonlinear teleoperators using predictor observers

This paper presents a delay compensation technique for nonlinear teleoperators by developing a predictor type sliding mode observer (SMO) that estimates future states of the slave operator. Predicted states are then used in control formulation. In the proposed scheme, disturbance observers (DOB) are also utilized to linearize nonlinear dynamics of the master and slave operators. It is shown that utilization of disturbance observers and predictor observer allow simple PD controllers to be used to provide stable position tracking for bilateral teleoperation. Proposed approach is verified with simulations where it is compared with two state-of-the-art methods. Successful experimental results with a bilateral teleoperation system consisting of a pair of pantograph robots also validates the proposed method

3.6 GHz CMOS Ring Oscillator with Low Tune Voltage Sensitivity and Temperature Compensation

In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations on the frequency span has been tuned out by an IPTAT (inversely proportional to absolute temperature) current reference. In this work, using a coarse-fine tuning mechanism lowers the tune range sensitivity of the oscillator, which is usually represented as Kvco. The achieved Kvco is around 490 MHz/V with 400 mV tune voltage sweep. The area and the power consumption of the ring oscillator are 0.0056 mm2 and 0.9 mW

Full Swing 20 GHz Frequency Divider with 1 V Supply Voltage in FD-SOI 28 nm Technology

In this paper we present the design of a pro- grammable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide- by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation speed. The proposed circuit achieves a maximum operating frequency of 20 GHz at 1 V supply voltage. And the area and the power consumption of the programmable divider are 1815 μm2 and 4.35 mW, respectively

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of the Re Ram cell depending on a clock input voltage level; a pull down transistor configured to set a first voltage level at the minus voltage node to a logically low voltage level if the data input is not connected to the plus and minus voltage nodes of the Re RAM cell; a bias circuitry configured to provide a fix bias current to set a second voltage level at the plus voltage node to a varying voltage level depending on the resistor value of the Re RAM cell if the data input is not connected to the plus voltage node; and a threshold adjusted circuitry arranged to convert an analog value of the second voltage level into a digital value and configured to generate an output signal and / or an inverted output signal

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, time and cost effective integration technique and at the same time provide device stability with CMOS-compatible materials that are used in the relevant device applications. In this study, we demonstrate a technique for the nm-scale hybrid integration of ReRAM on the foundry-produced CMOS 180 nm technology chip. Tungsten (W), as a material of choice for vertical vias in CMOS circuitry, is employed as the ReRAM electrode. However, W oxidizes readily, having multiple oxidation states, which influences the device reliability. In particular, the generation of semi-stable oxides at the electrode/switching layer (W/HfO2) interface has a profound influence on device performance. To achieve reliable W-based integrated ReRAM, we modulated and controlled the W electrode oxidation within the different co-integrated ReRAM stacks by increasing HfO2 switching layer thickness, through the post-metallization annealing under O-2-ambient, and by adding an Al2O3 barrier layer between the W and HfO2 layers. The effect of W interface modifications is further studied through the analysis of switching mechanism and TEM micro-structural characterization. A notable improvement in HRS/LRS resistance ratio and switching stability was observed in optimally fabricated (W/Al2O3/HfO2/TiN) ReRAM on the back end of the line (BEoL) of 180 nm CMOS chip